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NEW QUESTION: 1
組織には3つのAWSアカウントがあり、それぞれにバージニア、カナダ、シドニーの各地域にVPCが含まれています。 組織は、これらのアカウントで使用可能なすべてのElastic IPアドレス（EIP）が、コンプライアンスおよびコスト最適化の目的で、指定されたすべての地域でAmazon EC2インスタンスに接続されているか、使用中のElastic IP（ENI）であるかを判断します。
次のうちどれがLEAST管理オーバーヘッドの要件を満たしていますか？
A. AWS CloudFormation StackSetsを使用してすべてのアカウントおよび地域にAWS Config EIP添付ルールをデプロイし、未添付および未使用のEIPを見つけます。
B. 3つすべてのアカウントの各リージョンにAWS管理のEIP添付AWS Configルールを追加して、未添付および未使用のEIPを見つけます。
C. Amazon CloudWatchイベントルールを使用して、3つすべての地域の各アカウントでAWS Lambda関数をスケジュールし、未添付および未使用のEIPを見つけます。
D. CloudWatchイベントバスを使用して、3つの地域すべての各アカウントでLambda機能をスケジュールし、未接続および未使用のEIPを見つけます。
Answer: B
Explanation:
Explanation
https://docs.aws.amazon.com/config/latest/developerguide/eip-attached.html

NEW QUESTION: 2
What is the name of the core-to-core transport mechanism used in Intel XEON processors?
A. Crossbar switch
B. Quick Path Interconnect
C. Northbridge
D. Hyper Transport
Answer: B
Explanation:
The way I understand it, Crossbar is not a technology name, but a switch that assist in communication between processors, memory etc, allowing inter core & inter CPU communication. QPI, FSB & HT are all types of connections, connected to crossbar switches. All the answers are connected to crossbards, but only Intel has QPI. I would still go with QPI
www.site.uottawa.ca/~mbolic/ceg4131/Report Crossbar switches.pdf
A. Intel Xeon 7500 architecture The Intel Xeon 7500 series processor architectures uses an 8 port crossbar switch which implements the Intel QuickPath Interconnect (QPI) and routing layers. The Intel QPI is point-point interconnection link developed by Intel [1] to compete with HyperTransport. Prior to using QPI the Intel architecture was using the Front Side Bus (FSB) [2] which was the bus that carried data between CPU and the memory controller (northbridge) and I/O controller(southbridge).
The off-chip single memory controller often was the bottleneck which prevented faster CPUs from improving the overall performance of the system. Now, with crossbar implementation the microprocessor were able to integrate the northbridge on-chip for faster access As well: (Thanx MaaShar from Belgium)
http://www.intel.com/content/www/us/en/io/quickpath-technology/quickpath-technology- general.html
Intel@ QuickPath Technology uses Intel@ QuickPath Interconnect, which provides high-speed, point-to-point links inside and outside of the processor. In contrast to parallel buses, these links speed up data transfers by connecting distributed shared memory, the internal cores, the I/O hub, and other Intel@ processors.

NEW QUESTION: 3
Which interface provides heartbeat messages between the VSM and VEM?
A. backplane
B. packet
C. SVI
D. management
E. control
Answer: E